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AT86RF232
7.2.3.1 Description of RX_AACK Configuration Bits
Overview
Table 7-5 summarizes all register bits which affect the behavior of an RX_AACK
transaction. For address filtering it is further required to setup address registers to
match the expected address.
Configuration and address bits are to be set in TRX_OFF or PLL_ON state prior to
switching to RX_AACK mode.
A graphical representation of various operating modes is illustrated in Figure 7-11 .
Table 7-5. Overview of RX_AACK Configuratio n Bits.
Register
Address
0x20,0x21
0x22,0x23
0x24
…
0x2B
0x0C
0x17
0x17
0x17
Register
Bits
7
1
2
4
Register Name
SHORT_ADDR_0/1
PAN_ADDR_0/1
IEEE_ADDR_0
…
IEEE_ADDR_7
RX_SAFE_MODE
AACK_PROM_MODE
AACK_ACK_TIME
AACK_UPLD_RES_FT
Description
Set node addresses.
Protect buffer after frame reception.
Support promiscuous mode.
Change auto acknowledge start time.
Enable reserved frame type reception,
needed to receive non-standard compliant
frames.
0x17
5
AACK_FLTR_RES_FT
Filter reserved frame types like data frame
type, needed for filtering of non-standard
compliant frames.
0x2C
0
SLOTTED_OPERATION
If set, acknowledgment transmission has
to be triggered by pin 11 (SLP_TR)
0x2E
3
AACK_I_AM_COORD
If set, the device is a PAN coordinator,
that is responds to a null address.
0x2E
0x2E
4
5
AACK_DIS_ACK
AACK_SET_PD
Disable generation of acknowledgment.
Set frame pending subfield in Frame
Control Field (FCF), refer to
Section 8.1.2.2 .
0x2E
7:6
AACK_FVN_MODE
Controls the ACK behavior, depending on
FCF frame version number.
The usage of the RX_AACK configuration bits for various operating modes of a node is
explained in the following sections. Configuration bits not mentioned in the following two
sections should be set to their reset values according to Table 14-2 .
All registers mentioned in Table 7-5 are described in Section 7.2.6 .
The general behavior of the “ Atmel AT86RF232 Extended Feature Set”, Chapter 11 ,
settings:
o ANT_DIV
o RX_PDT_LEVEL
(Antenna Diversity)
(blocking frame reception of lower power signals)
are completely independent from RX_AACK mode and can be arbitrarily combined.
49
8321A – MCU Wireless – 10/11
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